The present invention generally relates to a method of fabricating a semiconductor element and more particularly, to a method of fabricating an insulating gate type field-effect transistor.
In the insulating gate type field-effect. transistor utilized in semiconductor integrated circuits in current use, hot carrier is produced by sharp electric field caused in the direction of the channel due to further miniaturization of elements, thereby resulting in deterioration of characteristics of the elements.
In order to mitigate concentration of electric field in the vicinity of a boundary between a channel region and a drain region subjected to a high voltage for the purpose of preventing deterioration of characteristics of the elements, a lightly doped drain (LDD) structure shown in FIG. 3 in which a region 10 having a low carrier density is provided between a source/drain region 13 having a high carrier density and a channel region disposed below a gate electrode 9 or a gate overlap structure shown in FIG. 4 in which a region 17 having a low carrier density for mitigating electric field as in the LDD structure is provided below a gate electrode 16 by oblique ion implantation so as to overlap the gate electrode 16 is employed.
Conventionally, the LDD structure is fabricated as shown in FIGS. 5(a) to 5(c). Initially, the region 10 having a low carrier density is formed by performing ion implantation at low density as shown in FIG. 5(a). Then, as shown in FIG. 5(b), an insulating film 11 is deposited on the gate electrode 9. Subsequently, the insulating film 11 is etched so as to form a pair of side walls 12 on the gate electrode 9. When ion implantation is performed at high density by using the side walls 12 as a mask, the source/drain region 13 having a high carrier density is formed. As a result, the region 10 having a low carrier density is formed between the channel region disposed below the gate electrode 9 and the source/drain region 13 having a high carrier density as shown in FIG. 5(c).
Meanwhile, the gate overlap structure employing oblique ion implantation is fabricated as shown in FIGS. 6(a) to 6(c). Initially, the region 17 having a low carrier density is formed by oblique ion implantation as shown in FIG. 6(a). Thereafter, an insulating film 18 is deposited on the gate electrode 16 as shown in FIG. 6(b). Subsequently, the insulating film 18 is etched so as to form a pair of side walls 19 on the gate electrode 16. When ion implantation is performed at high density by using the side walls 19 as a mask, the source/drain region 20 having a high carrier density is formed and thus, the region 17 having a low carrier density is formed below the gate electrode 16 so as to overlap the gate electrode 16. In the gate overlap structure, a method is proposed in which ion implantation at high density is performed without forming the side walls 19. However, in this method, leakage current increases due to damage caused by ion implantation at high density. In this respect, it may be preferable that the side walls 19 be formed.
In the above mentioned methods for producing the LDD structure and the gate overlap LDD structure, the steps of depositing the insulating film, etching the insulating film and performing ion implantation at low density are added in comparison with an insulating gate type field-effect transistor of ordinary structure. Thus, especially, such problems as damages to active layers by dry etching at the time of etching of the insulating film and defects caused by production of stress due to improper shape of the side walls arise.
Furthermore, conventionally, in the case where a complementary metal-oxide-semiconductor (CMOS) device having the LDD structure is fabricated, polysilicon gates are, respectively, formed initially on an n-channel metal-oxide-semiconductor (NMOS) region and a p-channel metal-oxide-semiconductor (PMOS) region which are provided on a substrate. Then, by implanting n type impurities and p type impurities, n.sup.- type regions are formed on opposite sides of the polysilicon gate in the NMOS region, while p.sup.- type regions are formed on opposite sides of the polysilicon gate in the PMOS region. Each time the above ion implantation is performed, photolithography is performed such that n type impurities and p type impurities are not implanted into the PMOS region and the NMOS region, respectively. Then, a silicon dioxide (SiO.sub.2) film is deposited on a wafer and is subjected to anisotropic etching such that a pair of side walls (spacers) made of silicon dioxide are formed on opposite sides of each of the polysilicon gates. Subsequently, by performing ion implantation, a source-drain region (n.sup.+ type region) is formed at a location spaced a distance approximately equal to thickness of the side walls from the polysilicon gate in the NMOS region, while a source-drain region (p.sup.+ type region) is formed at a location spaced a distance approximately equal to thickness of the side walls from the polysilicon gate in the PMOS region. Each time the above ion plantation for the n.sup.+ type and p.sup.+ type regions is performed, photolithography is performed such that n type impurities and p type impurities are not implanted into the PMOS region and the NMOS region, respectively in the same manner as in formation of the n.sup.- type and p.sup.- type regions. Thereafter, in order to repair damages caused by ion implantation, the n.sup.- type and p.sup.- type regions and the n.sup.+ type and p.sup.+ type regions are annealed concurrently. This annealing is performed relatively powerfully, i.e. at a relatively high temperature on the basis of the n.sup.+ type and p.sup.+ type regions sustaining great damage.
However, the steps of the above mentioned known fabrication method are excessively complicated in that the photolithography step is carried out each time ion implantation is performed and further, the side walls are formed by etching. Furthermore, since annealing is performed relatively powerfully on the basis of the n.sup.+ type and p.sup.+ type regions, impurities in the n.sup.- type and p.sup.- type regions are diffused excessively and thus, transistor characteristics are deteriorated by short channel effect of transistors.